1. Field
Apparatuses, devices, controllers, and systems consistent with the present inventive concept relate to a memory device, and more particularly, to a memory device for controlling an activation timing of a control signal for operating the memory device using a variable delay circuit and systems including the same.
2. Description of the Related Art
Semiconductor devices are divided into static random access memory (SRAM) that stores data using a latch and dynamic random access memory (DRAM) that stores data using a capacitor.
As the size of an SRAM cell decreases with the development of process technology, the distribution of a basic process characteristic of a transistor included in the memory cell increases and the distribution of an SRAM characteristic such as a write margin, a static noise margin or a sense margin also increases.
Due to these phenomena, an operation error occurs when an SRAM is operated using a delay set in the design stage. Since the delay cannot be changed in a related art SRAM, an SRAM having the operation error is rejected as faulty. As a result, the yield of the SRAM decreases.